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Lithoguru Search Primary Menu Search for: General Robert H. Dennard, 1932 – 2024 May 10, 2024 Chris Leave a comment Robert (Bob) Dennard, inventor of the DRAM and Dennard scaling, died on April 23, 2024. I never met Bob, but heard many stories from his IBM colleagues who said he was universally loved and admired. The comment that sticks with me from several people who worked with him: every time you saw Bob Dennard he always had a smile on his face. Here is his obituary: https://www.lohud.com/obituaries/pnys0809210 Bob Dennard Microlithography SPIE Advanced Lithography and Patterning Symposium 2024 – day 4 March 1, 2024 Chris Leave a comment The final day! In the morning I watched the ASML updates on their EUV and DUV systems, working backwards from high-NA EUV. Two high-NA systems are being put together almost simultaneously, one at the High-NA demonstration lab in Veldhoven, and one at Intel in Portland. These tools should start running wafers at resolution in a few weeks or months”, according to Jara Garcia-Santaclara. Since design work began in 2014, a 10-year idea-to-print cycle is pretty good for a tool of this complexity. On the low-NA EUV front, the new NXE:3800 has started shipping (though none are yet running at a customer site), with a 25% increase in source power and other changes to increase throughput and performance. Anyone who has been paying attention knows that financial analysts have been coming regularly to this symposium for at least 20 years. The consequences are never good. Companies that care about their stock price (and that would be all companies that have a stock price) often require their authors to provide messages that they want to give to Wall Street, regardless of how it plays to the lithography community. A perfect example was Peter Klomp, who gave a good talk on ASML’s low-NA EUV tools. But it was padded with 6 or 8 slides at the front that were completely unnecessary for the lithography community and sounded like the kind of thing a CEO would say at the start of an investors’ day event. Data is growing! AI is coming! People need more chips! Ah well. Yoji Watanabe of Nikon talked about their development of maskless DUV projection systems (both 248 and 193nm) using a digital mirror spatial light modulator in place of the mask. They have a proof-of-concept system running, and some of its parameters were revealed. It has a 193 nm wavelength with NA = 0.675. The reduction ratio is greater than 100” resulting in an exposure field less than 1 mm wide. The pixel size at the wafer is 40 nm, and the current throughput is 0.5 wafers per hour. Obviously all of these things will evolve (smaller pixel size, larger field size, higher throughput) as development proceeds, but the initially images looked pretty good. There are definitely some devices where mask costs exceed most all other costs, so I can see the benefits of such a maskless system. Chris Anderson of xLight shed some light on that start-up’s audacious plans for building Free Electron Laser (FEL) light sources for EUV manufacturing. While everything they have is still only on paper (they are shooting for first light in 2027), he described a centralized FEL (a pair of them actually) that could feed up to 20 EUV scanners with 2kW of power (4X greater than the brightest sources currently available from ASML). The cost of one of these sources would be about $500M (give or take a few $100M), so that is a pretty big bet, especially since ASML will get to decide if xLight even has a chance to compete. After zipping over to the Directed Self-Assembly (DSA) session in the Novel Patterning conference, I learned from Lander Verstraete of imec that contact hole rectification with DSA is great in about all respects except one – local pattern placement error (LPPE). While local CD Uniformity (LCDU) significantly improves after applying DSA (enabling low-dose EUV printing of the original holes), the LPPE gets worse. Further optimization is required – I doubt it is a fundamental problem. Tomoshiro Iwaki of Micron spoke ing DSA with 9X multiplication (3X pitch division in both X and Y) when printing staggered arrays of holes. Iwaki-san presented a year’s worth of 1b DRAM yield data, showing an improvement up to the current 88.5% yield. Still, the process is not in high-volume manufacturing for reasons that Iwaki-san was a bit cagey about, but I think related to the pattern placement error of the holes. Rober Browning of Intel gave a short but sweet talk on using the Applied Materials Sculpta tool to shrink tip-to-tip spacing for the case of trenches (common to damascene metal layers). The tool uses physical etching at an angle to preferentially increase etch bias in only one direction, and Intel used it to grow the length of a space without growing its width. In Intel’s case they were able to replace an EUV double exposure process with a single exposure + Sculpta. Very interesting, and it sounded like Intel has proven out its potential. I left the conference to go home a few hours early, and so missed some good papers (including one I was a coauthor on with Ben Bunday). As always, it was a fun but exhausting week. The mood was upbeat, as the industry recovers from its 2023 doldrums. 2024 is off to a good start! Mircrolithography SPIE Microlithography SPIE Advanced Lithography and Patterning Symposium 2024 – day 3 February 29, 2024 Chris Leave a comment Wednesday was the peak of busy for me, attending many papers (and giving one). It was also a very typical day in that almost all of the papers I saw were exactly what I expected: incremental advances. Nothing jaw dropping, just the small advances that have fueled this industry’s progress for the 40 years I have been involved. Jodi Grzeskowiak of TEL did a great job explaining their new anti-spacer” process, using acid diffusion into a resist pattern to form a skin that turns into a negative tone version of a spacer pattern. She described it as a track-based pitch split.” I was especially happy that the process didn’t have a cute acronym with a trademark symbol and no description of how it worked. Indira Seshadri of IBM showed off what IBM is good at, optimizing all aspect of a process (in this case the Lam dry resist) to get high yield at tight pitches. Hyeon Bo Shim of Samsung provided a simple geometric model for how electrons escape out of a contact hole (for the case of vertical sidewalls only), showing that the aspect ratio controls the visibility of the hole bottom. Since I am a coauthor (with Ben Bunday) on a paper on a similar topic on Thursday, I was especially interested. I’ve already checked out this Samsung geometric model against our SEM simulations and it works surprisingly well. Boris Habets (KLA) collected overlay data on the micron scale”. He was able to measure overlay directly on the device, but did so in a memory cell so that he could achieve extremely high sampling over length scales we don’t normally interrogate. Over a distance of a few microns overlay variations are not due to scanner effects, but rather shorter-range proximity effects. In this case, each memory array tile (a few microns square) had a regular signature, possibly due to film stress relaxation. The magnitude was a few tenths of a nanometer, but if stable and consistent would be correctable on the mask. I attempted to attend the panel discussion on the future of EUV lithography, but was unsuccessful. The event was standing room only, and I was unwilling the elbow my way through the crowd standing three deep at the door. I hope it was useful. I did make it to the poster session, however, and actually walked the whole circuit. There were some nice posters and a fun crowd. Mircrolithography SPIE Microlithography SPIE Advanced Lithography and Patterning Symposium 2024 – day 2 February 28, 2024 Chris 2 Comments The plenary session was split into two days this year, with two plenaries on Tuesday morning. Ann Kelleher of Intel talked about her view of...